1. Field of the Invention
The present invention relates to an ESD (Electrostatic Discharge) protection circuit, and more particularly relates to an ESD protection circuit that can save area and prevent leakage current.
2. Description of the Prior Art
FIG. 1 illustrates a prior art ESD protection circuit 100. As shown in FIG. 1, the prior art ESD protection circuit 100 can include ESD protection devices 101, 103, trigger circuits 107, 109 and an ESD detection circuit 111. The object of such structure is to avoid the ESD voltage directly entering the internal circuit 105 via the input/output pad 113 to damage the internal circuit 105, when the ESD voltage is generated. The operation of the ESD protection circuit 100 can be summarized as below: the ESD detection circuit 111 generates a control signal to control the triggering circuits 107 and 109, when the ESD detection circuit 111 detects the ESD voltage is generated. Then, the trigger circuits 107 and 109 will trigger the ESD protection devices 101, 103, such that the ESD protection devices 101, 103 can guide out the ESD current, thereby the internal circuit 105 can be protected.
However, the trigger circuit 107 will occupy a large area, and a trigger circuit must be provided for each ESD protection device in this kind of structure. Accordingly, the trigger circuit 109 will also occupy a large area. Additionally, in order to decrease the complexity and the cost of the chip, devices with thin oxide layers are always utilized to implement the ESD detection circuit and the trigger circuit. In this situation, leakage current ILEA may occur and flow along the path shown in FIG. 1 to the voltage Vss. Also, the leakage current will cause extra power consumption when the internal circuit 105 operates normally.